General Description: When doing an FSM in State Editor for VHDL, there are 2 places where the user may choose the FSM encoding scheme: * Synthesis -> Options or * FSM -> Machines -> <fsm_name> (Machine Properties dialog box)
Only the latter method has any effect on the synthesized design. State Editor uses the Synopsys attributes package to explicitly define the encoding, and therefore the synthesis options' FSM extraction encoding option doesn't have any effect.
When setting the desired encoding scheme for the State Machine, use the following methodology:
FSM -> Machines -> <machine_name>
Choose the appropriate encoding scheme in the Machine Properties dialog.