Description: When using FPGA Express, one may use the Express Constraints Editor to select clock buffers to be place on input ports for clock and high fanout signals.
In some cases for XC9500 designs, the FPGA Express Constraints Editor will not allow the selection of the BUFG. Only BUFGTS and BUFGSR are available.
解决方案
The workaround is to instantiate a BUFG in the HDL code.