General Description: FPGA Express always uses the LD_1 component when a latch is inferred in the HDL code. This may result in inefficient implementations if the latch includes a local reset or clock enable.
The only work-around is to instantiate the specific latch primitive desired. These components include LD, LDC, LDC_1, LDCE, and LDCE_1.
Consult the Xilinx Libraries Guide for a list of latch primitives for each family.