While compiling the timing simulation netlist produced by version 1.5 (or later) of the Xilinx software, the following error may occur:
ERROR: time_sim.vhd(###): Type error in bit string literal. Type string is not an array of bit.
This error message is generally caused by simulating a 1.5 (or later) simulation netlist with the Xilinx 1.4 (or earlier) libraries. There was a change in the way RAM is initialized moving from the 1.4 to the 1.5 software release. Due to this change, the libraries must be recompiled using the 1.5 version of the libraries to simulate a 1.5 version of the timing netlist.
See (Xilinx Solution 1923) for details on re-compiling the Xilinx libraries for the Model Technology Modelsim simulator.