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AR# 4993

V1.5 CORE Generator, VERILOG-XL - "Error! syntax error...parameter signed=<..."


Keywords: Verilog, CORE Generator, COREGen, syntax, error

Urgency: Hot

General Description:
The following error may be seen when loading a CORE Generator
Verilog behavioral model involving signed data
(SDA FIR filters, adders, subtractors, multipliers, etc.):

" Error! syntax error [Verilog]
"add20.v", 19: parameter signed =<-"

The syntax error being flagged in the error message is that
you have illegally specified the Verilog-XL reserved word,
"signed", as one of your user parameters.

The problem line of code in the CORE Generator behavioral model is
the following:

parameter signed = `true;


As a work-around, all instances of the word "signed", where
it is used as a user parameter, should be replaced with a
non-reserved word (for example, "signed_data") using a text editor.
AR# 4993
日期 02/15/2001
状态 Archive
Type ??????