General Description: When black boxes are instantiated in a Verilog design (for LogiBLOX and CoreGen, for example), a module declaration is required to let Express know the port directions and sizes. If this module declaration is missing, the clock pin may be left out of the instantiation.
For LogiBLOX and CoreGen designs, use the .VEI file to obtain the module declaration. Only the portion of this file from the "module" to "endmodule" keywords is necessary. For other black boxes, this declaration must be written by the user.
This declaration can exist in any of the Verilog files added to the project, or within its own unique .V file. It should look like the following: