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AR# 50154

LogiCORE IP Asynchronous Sample Rate Converter (ASRC) v1.0 - Why does the core not behave as expected when Verilog generation is selected?

描述

Why does the core not behave as expected when Verilog generation is selected?

解决方案

This is a known issue where the GUI parameters MAX_COUNT and FIFO_SET_POINT are not being properly passed down to the Verilog wrapper file (*_synth.v). There is also a problem where the shift_reg_27x16.v is missing a statement in the generate statement.

These issues have been address in ISE 14.3 Asynchronous Sample Rate Converter (ASRC) v1.0. You can regenerate Asynchronous Sample Rate Converter (ASRC) v1.0 in 14.3 and later, and these changes will be automatically included.

To work around this issue, change *_synth.v (lines 71-73):

From:
.C_FAMILY("virtex6"),
.FIFO_SET_POINT(000010000),
.MAX_COUNT(00001111111111)

To:
.C_FAMILY("virtex6"),
.FIFO_SET_POINT(16),
.MAX_COUNT(1023)

And change shift_reg_27x16.v (line 70):

From:
begin

To:
begin:shift_reg_gen

For a detailed list of LogiCORE IP Asynchronous Sample Rate Converter (ASRC) Release Notes and Known Issues, see (Xilinx Answer 47209).

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
47209 LogiCORE IP Asynchronous Sample Rate Converter (ASRC) - Release Notes and Known Issues N/A N/A
AR# 50154
日期 01/16/2013
状态 Active
Type 综合文章
器件
  • Spartan-6
  • Virtex-6
IP
  • Asynchronous Sample Rate Converter (ASRC)
的页面