描述

If source and destination clocks are the same, the clock uncertainty used in the hold time analysis is 0, but the setup time analysis uses a positive clock uncertainty value. Why?

Slack (setup path): 0.014ns (requirement - (data path - clock path skew + uncertainty))
Source: clock_control/reset156_0 (FF)
Destination: top_10g_c/xge_interface/xaui_block/xaui_core/BU2/U0/G_XGMII.G_ELASTIC_BUFFER.elastic_buffer_i/asynch_fifo_i/rd_truegray_0 (FF)
Requirement: 6.200ns
Data Path Delay: 6.114ns (Levels of Logic = 0)
Clock Path Skew: -0.007ns (1.863 - 1.870)
Source Clock: clk156m_ref rising at 0.000ns
Destination Clock: clk156m_ref rising at 6.200ns
Clock Uncertainty: 0.065ns

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

Slack (hold path): 0.010ns (requirement - (clock path skew + uncertainty - data path))
Source: top_10g_b/xge_interface/rxaui_block/rxaui_core/BU2/U0/xaui_i/transmitter/recoder/txd_out_17 (FF)
Destination: top_10g_b/xge_interface/rxaui_block/gtx_wrapper_i/gtx1_gtx_wrapper_i/gtxe1_i (HSIO)
Requirement: 0.000ns
Data Path Delay: 0.330ns (Levels of Logic = 0)
Clock Path Skew: 0.320ns (2.084 - 1.764)
Source Clock: clk156m_ref rising at 6.200ns
Destination Clock: clk156m_ref rising at 6.200ns
Clock Uncertainty: 0.000ns

解决方案

If source and destination clocks are the same clock net, the hold time is analyzed between the same clock edge.

Source Clock: clk156m_ref rising at 6.200ns
Destination Clock: clk156m_ref rising at 6.200ns

The clock jitter applies uniformly to both the source and destination clock arrival times, so no clock uncertainty between the source and destination clocks. As a result, the clock uncertainty is calculated as 0.