Please see the main Performance article for more information on I/O performance (Xilinx Answer 47284).
This Answer Record covers the following:
Differential I/O standards:Differential signaling is a method of transmitting data between two devices using two complementary signals, sent on two separate traces.
For outputs, Xilinx specifies a range of values for the common mode output voltage. This is the value of the 'common' voltage that the two signals in the pair vary around.
We also specify the difference in the voltage of the two signals in the pair. It is given by Vp-Vn when Vp is high and Vn - Vp when Vn is high.
Xilinx also gives the VOL and VOH levels. VOL is the minimum output voltage for each of the signals, and VOH this is the maximum output voltage for either of the signals in the pair.
These specifications must be compared to the corresponding specification at the transmit/receive device to ensure that the link will work.
Shown here is a LVDS signal: The Common mode, differential Swing and VOL VOH are shown.
In many cases, the differential input does not operate in the bank VCCO domain. This can give extra flexibility when placing differential input buffers.
This is discussed in (Xilinx Answer 11906).
You should also look at these two answers for guidance on placing LVDS in different 7 Series bank types:
(Xilinx Answer 40191) - LVDS Compatibility Between LVDS_25 and LVDS.
(Xilinx Answer 41408) - How to Place LVDS in a High Performance Bank.