Is a bitstream generated for JTAG configuration the same as a bitstream for other configuration modes, such as SelectMap or Master Serial?
The XC4000E, XC4000EX, and XC5200 can all be configured through the TAP. The configuration process is virtually identical to the non-JTAG/BOUNDARY Scan configuration process, except the interface to the FPGA is done through the TAP.
The ".bit" file or ".rbt" file can be used to configure the XC4000E, XC4000EX, and XC5200, via the JTAG TAP, without any special modifications.
For the Virtex device and its derivatives, care should be taken for the "startupclk" option in BitGen.
Generally, startup clock is specified to be JTAGCLK for BSCAN configuration and CCLK for Serial or SelectMap configuration. For more information, please refer to the user guide.