AR# 5023

SYNPLIFY: Why does disabling the "Force GSR usage" option still infer the STARTUP block? Using the xc_isgsr attribute?

描述

Keywords: Synplify, GSR, GR


Urgency: Standard

General Description:
Disabling the "Force GSR usage" option still infers the
STARTUP block. Why?

Synplify will infer the STARTUP block under the conditions
outlined in (Xilinx Solution 4034). However, Synplify 5.0.8
introduces a new attribute, xc_isgsr, to disable STARTUP
when the STARTUP exists in a pre-optimized (black-box)
netlist (XNF, EDIF, NGO) such as the PCI CORE. Please
see (Xilinx Solution 2713). Mark the port/signal of the core
which is connected to the GSR pin of the STARTUP.

解决方案

1

// Disable STARTUP inference using xc_isgsr
// Only for Synplify 5.0.8 and later
// Specifies that a reset pin on a black-box is connected to an
// internal STARTUP block

module IS_GSR_EX (A, B, C, D_IN, Q_OUT, RST, CLK);
input RST, D_IN, CLK, A, B;
output Q_OUT, C;

reg Q_OUT;

// Flip-flop with asynchronous reset
always @(posedge RST or posedge CLK)
if (RST)
Q_OUT <= 1'b0;
else
Q_OUT <= D_IN;

STARTUP_INSIDE U0 (.RST (RST), .A (A), .B (B), .C (C));

endmodule

module STARTUP_INSIDE (RST, A, B, C) /* synthesis black_box */;
input RST /* synthesis xc_isgsr = 1 */;
input A, B;
output C;

endmodule

2

SDC
---

Based on our earlier examples, the xc_isgsr attribute can be
passed in a SDC file.

define_attribute {U0.RST} xc_isgsr 1

3

-- Disable STARTUP inference using xc_isgsr
-- Only for Synplify 5.0.8 and later
-- Specifies that a reset pin on a black-box is connected to an
-- internal STARTUP block

library ieee, synplify;
use ieee.std_logic_1164.all;
use synplify.attributes.all; -- Define Synplify attributes

entity STARTUP_INSIDE is
port (RST, A, B : in std_logic;
C : out std_logic);
attribute xc_isgsr of RST : signal is true;
end STARTUP_INSIDE;

architecture BEHAVE of STARTUP_INSIDE is

attribute black_box of BEHAVE : architecture is true;

begin

end BEHAVE;


library ieee, synplify;
use ieee.std_logic_1164.all;
use synplify.attributes.all; -- Define Synplify attributes

entity IS_GSR_EX is
port (A, B, D_IN, RST, CLK : in std_logic;
C, Q_OUT : out std_logic);
end IS_GSR_EX;

architecture XILINX of IS_GSR_EX is

component STARTUP_INSIDE
port (RST, A, B : in std_logic;
C : out std_logic);
end component;

begin

-- Flip-flop with asynchronous reset
process (RST, CLK)
begin
if (RST = '1') then
Q_OUT <= '0';
elsif rising_edge(CLK) then
Q_OUT <= D_IN;
end if;
end process;

U0 : STARTUP_INSIDE port map (RST => RST, A => A, B => B, C => C);

end XILINX;
AR# 5023
日期 04/24/2007
状态 Archive
Type 综合文章