Version Found: 1.03.a
Version Resolved and other Known Issues: See (Xilinx Answer 44969)
When the value of C_NUM_MSI_REQ parameter in the MHS file is set to 16, the tool results in the following error message when implementing the design with AXI Bridge for PCI Express v1.03.a core.
Setting it to 16 (what is being used now) yields the following error during map:
ERROR:Pack:1130 - Symbol PCIEAXI.SREV1.PCIEAXIMM_R1/axi_pcie_bridge/axi_pcie_bridge/comp_axi_enhanced_pcie/comp_enhanced_core_top_wrap/axi_pcie_enhanced_core_top_i/k7_pcie_7x_v1_3_inst/pcie_top_i/pcie_7x_i/pcie_block_i of type PCIE_2_1 has a property "MSI_CAP_MULTIMSGCAP" with an illegal value of "16".
This is a known issue to be fixed in a future release of the core. The allowed values for C_MSI_REQ_NUM is from 0 to 5.
Set the paramter to '1' to request 1 MSI vector, '2' to request 4 MSI vectors, '3' to request 8 MSI vectors, '4' to request 16 MSI vectors and '5' to request 32 MSI vectors.
Revision History
06/04/2012 - Initial release
| Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
|---|---|---|---|
| 44969 | AXI Bridge for PCI Express - Release Notes and Known Issues for All Versions up to ISE 14.7 | N/A | N/A |
| AR# 50261 | |
|---|---|
| 日期 | 08/26/2013 |
| 状态 | Active |
| Type | 综合文章 |
| Tools | |
| IP | |