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AR# 50276

Virtex-7 FPGA Gen3 Integrated Block for PCI Express v1.1 (Vivado 2012.1) - Incorrect Capability Pointer Value

描述

Version Found: v1.1
Version Resolved and other Known Issues: See (Xilinx Answer 47441)

The generatedHDL file (inside 'synth' and 'sim' directories in Vivado core generation directory structure) has the *_CAPABILITY_POINTER value set to 'H20 instead of 'H80.

解决方案

This is a known issue to be fixed in a future revision of the core.

Note: "Version Found" refers to the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Revision History
06/04/2012 - Initial release

链接问答记录

主要问答记录

AR# 50276
日期 01/21/2013
状态 Active
Type 综合文章
Tools
  • Vivado - 2012.1
IP
  • Virtex-7 FPGA Gen3 Integrated Block for PCI Express (PCIe)
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