General Description: How to prevent the grouping of ports into arrays in the output EDIF netlist using the syn_noarrayports attribute?
The syn_noarrayports attribute specifies that the ports on a design unit should be left as scalars and not grouped into an array (bus) notation during synthesis. This should be applied to the top level entity or module.
See also (Xilinx Solution 2649) on information on modifying the bus-notation in an EDIF generated netlist.
解决方案
1
VHDL ----
library synplify, ieee; use synplify.attributes.all; use ieee.std_logic_1164.all;
entity TOP is port (A, B : in std_logic_vector(7 downto 0); CIN : in std_logic; SUM : out std_logic_vector(7 downto 0); COUT : out std_logic); attribute syn_noarrayports of TOP : entity is true;