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AR# 50430

Zynq 7000 - PlanAhead / ISE Design Suite - XST:528 Multi-Source Warnings on PS_SRSTB, PS_CLK, PS_PORB

描述


If implementing a Zynq FPGA design in the PlanAhead tool or ISE Design Suite 14, XST outputs the following warnings whenever the design is synthesized:

WARNING:Xst:528 - Multi-source in Unit <system_processing_system7_0_wrapper> on signal <PS_SRSTB>; this signal is connected to multiple drivers.
Drivers are:
Primary input port <processing_system7_0_PS_SRSTB_pin>
Output port PS7:PSSRSTB of instance <processing_system7_0/processing_system7_0/PS7_i>

WARNING:Xst:528 - Multi-source in Unit <system_processing_system7_0_wrapper> on signal <PS_CLK>; this signal is connected to multiple drivers.
Drivers are:
Primary input port <processing_system7_0_PS_CLK_pin>
Output port PS7:PSCLK of instance <processing_system7_0/processing_system7_0/PS7_i>

WARNING:Xst:528 - Multi-source in Unit <system_processing_system7_0_wrapper> on signal <PS_PORB>; this signal is connected to multiple drivers.
Drivers are:

Primary input port <processing_system7_0_PS_PORB_pin>
Output port PS7:PSPORB of instance <processing_system7_0/processing_system7_0/PS7_i>

解决方案


In the device model, the direction for these ports in "system_i/processing_system7_0/processing_system7_0/PS7_i" is defined as an IN/OUT port and the wrapper file generated by the XPS project and the "processing_system.v" has the direction definition as "IN". This results in the multiple driver warnings during synthesis.

These warnings can be ignored in the current releases.

This issue is expected to be resolved in a future release of the Xilinx tools.
AR# 50430
日期 11/07/2012
状态 Active
Type 综合文章
器件
  • Zynq-7000
  • ??????
Tools
  • PlanAhead
  • ISE
  • ISE Design Suite - 14
  • More
  • ISE Design Suite
  • ??????
  • Less
IP
  • Processing System 7
  • ??????
的页面