描述

解决方案

Modifications to the 10G PCS-PMA core used in the Kintex-7 FPGA Connectivity Kit TRD include:

- To use two instances of the IP, the GT wrappers for two GT sharing a quad and not sharing a quad have been generated separately

- For use of 312.5 MHz clock provided by FMC, the parameter QPLL_REFCLK_DIV is changed to 2 in files:
'ip_cores/xphy_gt_wrapper/gtwizard_10gbaser_same_quad.v' and
'ip_cores/xphy_gt_wrapper/gtwizard_10gbaser_diff_quad.v'

- MMCM is used to derive 156.25 MHz for XGEMAC

- In addition to (Xilinx Answer 45360) suggested changes, the following attributes are also updated:
RX_CLKMUX_PD = 1 (xphy_gt_wrapper/gtwizard_*_quad_gt.v)
TX_CLKMUX_PD = 1 (xphy_gt_wrapper/gtwizard_*_quad_gt.v)

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