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AR# 50570

14.x TRCE - Does OFFSET OUT with REFERENCE_PIN report Max and Min output delays between the output data and the output clock?


If I use OFFSET OUT constraint withthe REFERENCE_PIN, I get the following information for the Slowest and Fastest paths.However, this is not the skew between the output data and output clock.

Where is the output bus skew associated with the output clock?


To getthe information for theMax and Minoutputskew between theoutput clock and the output data, it is necessary to check the"Data sheet" section in the Timing report.

Inside this section you will find a table reporting the delays (skews) between the output data and the output clock.
However, the delays in this tableare referred only to the "Slowest paths" analysis, which is the maximum delay between the output clock and the output data.

AR# 50570
日期 10/12/2012
状态 Active
Type 综合文章
  • FPGA Device Families
  • ISE Design Suite
  • ISE Design Suite - 14
  • ISE Design Suite - 13
  • More
  • ISE Design Suite - 12
  • ISE Design Suite - 11
  • Less