UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 50633

AXI Bridge for PCI Express - Root Port Implementation does byte swap to the completion packet for a configuration read issued to an Endpoint device

描述

Version Found: v1.03a, v1.04a
Version Resolved and other Known Issues: see (Xilinx Answer 44969)

When operating in Root Port mode, if configuration read packets were sent to an Endpoint device, the returned completion from that configuration read will be byte-reversed by the AXI_PCIe bridge of the Root Controller.

解决方案

The example Root Controller driver provided by Xilinx will automatically handle this situation. Users who write their own driver should be aware of this issue and make sure that their driver handles this issue correctly.

This information will be added into the next release of the documentation.

Revision History
07/25/2012 - Initial release

Note: The "Version Found" column lists the version in which the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
44969 AXI Bridge for PCI Express - Release Notes and Known Issues for All Versions up to ISE 14.7 N/A N/A
AR# 50633
日期 01/21/2013
状态 Active
Type 已知问题
Tools
  • EDK - 14.1
  • EDK - 14.2
IP
  • AXI PCI Express (PCIe)
的页面