2. 技术支持
  3. AR# 5063: M1.5/Synopsys - FPGA designs containing STARUP/STARTBUF component may not configure properly when using FPGA/Design Compiler
  4. AR# 50634: AXI Bridge for PCI Express - Memory Write to address 0x0000_0000 is treated as an MSI Request in Gen1X8 and Gen2X4 Endpoint configuration

AR# 50634

AXI Bridge for PCI Express - Memory Write to address 0x0000_0000 is treated as an MSI Request in Gen1X8 and Gen2X4 Endpoint configuration

描述

Version Found: v1.03a
Version Resolved and other Known Issues: see (Xilinx Answer 44969)

If I attempt to perform a write (Memory Write) to address 0x0000_0000, the request is mistaken as an MSI request. The core should never look for a MSI request when in Endpoint configuration.

解决方案

This is a known issue that is scheduled to be fixed in theISE 14.3release of the core.

To work around the problem, you can add the following expression into the axi_enhanced_rx_demux module where pkt_addr == msi_address && pkt_typr[4] == 1'b 0:

&& C_ROOT_PORT == TRUE

Modified code:

if(pkt_addr == msi_address && pkt_typr[4] == 1'b 0 && C_ROOT_PORT == TRUE) begin

Revision History
7/25/2012 - Initial release

NOTE: The "Version Found" column lists the version in which the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
44969 AXI Bridge for PCI Express - Release Notes and Known Issues for All Versions up to ISE 14.7 N/A N/A
AR# 50634
日期 10/23/2012
状态 Active
Type 已知问题
IP