描述

This Release Notes and Known Issues answer record is for the Memory Interface (MIG) v3.92 release in the ISE Design Suite 14.3 and contains the following information:

• General Information
• Software Requirements
• New Features
• Resolved Issues
• Known Issues

For installation instructions, general CORE Generator known issues, and design tools requirements, see the Release Notes Guide.

解决方案

General Information

The MIG Virtex-6 and Spartan-6 v3.92 products are available through ISE Design Suite 14.3. 

For a list of supported memory interfaces and frequencies for the Spartan-6 FPGA Memory Controller Block (MCB), see the following user guides:

• Memory Interface Solutions User Guide (UG388)

• Virtex-6 FPGA Memory Interface Solutions User Guide (UG406)
• Virtex-6 FPGA Memory Interface Solutions Data Sheet (DS186)

• ISE Design Suite 14.3 support

Resolved Issues
(Xilinx Answer 50615) MIG Spartan-6 v3.91 LPDDR: Incorrect termination upon reset
(Xilinx Answer 38731) MIG v3.5-v3.91, Virtex-6 DDR3 - Simulation - 'SKIP' Calibration Causes Errors in the Example Design
(Xilinx Answer 39423) MIG v3.6-v3.91 Virtex-6 DDR2/DDR3/QDRII+ - The VRN/VRP pins were occupied by controller I/Os which require another bank for DCI Cascade
(Xilinx Answer 50676) MIG v3.91 Virtex-6 DDR3/DDR2 - design fails when "Add I/O Buffers" option is used in XST
(Xilinx Answer 57343) MIG Spartan-6 DDR3 - UG416 lists the incorrect Reset Polarity for AXI MCB interface
(Xilinx Answer 57344) MIG Spartan-6 MCB - UG388 missing information on the EDK clock "ui_clk "
(Xilinx Answer 57359) MIG Virtex-6 DDR3 - Generating a MIG DDR3 core targeting a single rank x8 RDIMM results in two sets of incorrectly generated CS and ODT signals

Known Issues
(Xilinx Answer 63262) MIG Virtex-6 v3.92 DDR3 - SODIMM MT4JSF12864HZ-1G4 uses incorrect timing parameter values
(Xilinx Answer 54378) MIG Virtex-6 v3.92 QDRII+ - faulty DRC error during custom pinout validation
(Xilinx Answer 53701) MIG Virtex-6 DDR2 - Incorrect advancement of CS in 64-bits or wider component designs using less than five CK clocks
(Xilinx Answer 45740) MIG Spartan-6 MCB DDR2 - Example Design (Traffic Generator) exhibits data errors when using 6 ports or 4 ports
(Xilinx Answer 52177) MIG Virtex-6 v3.92 DDR3 - example design may fail timing when using the VHDL generated design
(Xilinx Answer 55538) MIG Virtex-6 - QDRII+ dbg_rd_stage1_cal connections incorrect in UG406
(Xilinx Answer 33613) MIG Virtex-6 DDR2 - Design incorrectly assigns app_wdf_mask (user interface data mask) to 0 preventing the ability to mask data                                                                                        

Revision History
09/04/2013 - Added 57359
04/17/2013 - Added 55538
02/21/2013 - Added 54378
01/08/2013 - Added 53701
10/02/2014 - Added 33613
01/08/2015 - Added 63262

链接问答记录

主要问答记录

子答复记录