This article will discuss using IBIS models to debug signal integrity issues in your design.
This article will discuss how IBIS models can be used to debug signal integrity issues.
If you are not familiar with IBIS models and want to learn more about how IBIS models are used to model I/O drivers and receivers, please see (Xilinx Answer 50653) IBIS Models & Simulation - IBIS Model Background
Logic levels :
One of the most useful things you can use an IBIS simulation for is to understand what voltage level is present at the receiver after the signal has passed through the PCB trace.
You can then ensure that the correct logic level is present at the receiver for it to detect a logic 0 or logic 1.
A simple example shows how the IBIS simulator can give details about logic levels at various operating points.
This very basic example contains a simple Virtex-6 LVCMOS25 with its slew rate set to slow with a 12mA drive strength driving another Virtex-6 LVCMOS25 input at the end of a short 50Ohm PCB trace.
In the first instance the I/O is being asked to drive a 50Mhz signal to the receiver. The slow signal is easily driven along the line and we can see if we probe the signal at the receiver that the signal is driven all the way to the rails.
As the speed is increased above 100Mhz, you can see that the driver is no longer able to drive the signal all the way to the rails because it is too weak. It is trying drive the line to the rail, but the driver switches to pull the line back down before this can happen.
At speeds like this the logic levels from the data sheet are being achieved. If the speed is increased beyond 200Mhz then even with the short trace the driver cannot operate this fast, as it cannot drive the line to a sufficiently high voltage to be seen as a logic 1 by the receiver.
In this way you can use the IBIS simulations to ensure that for a given driver, trace, and data rate, the driver will provide signals that meet the specified logic levels of the receiver.
To learn more about Xilinx I/O performance specifications please refer to (Xilinx Answer 47284)
If you have a Xilinx Device driving the line, you can use the trace and receiver information to select a driver that will provide correct logic levels at the receiver.
For more information on drive strength, please refer to (Xilinx Answer 38820).
Source and sink currents:
Another use is to look at source and sink currents. In this case the IBIS simulator is set up to probe current on both a rising edge in green and a falling edge in red.
The IBIS model can be used to examine the effect of different termination schemes on the signal. For any topology you have there will be reflections on the line caused by the propagating wave striking something at the far end. The effect of reflections at the receiver is as ringing or overshoot on the signal, or the signal appearing to have a staircase towards the steady value.
When a driver is too strong or its output impedance is less than that of the line, you will get the overshoot or ringing phenomenon at the receiver. When the driver is weak and it has an output impedance greater than that of the line, then you will get a staircase type edge at the receiver. For more details on termination and Xilinx I/Os, please refer to (Xilinx Answer 47225).
The IBIS models can be used to examine the effect of different termination schemes on the signal integrity of the design. A good example is a weak driver driving a line. You can see that in the example below the rising edge in pink does not rise up to the logic high level in a smooth fashion. It has a pronounced step in its rising edge. This is due to the reflection coming back from the receiver before the driver has been able to drive all the way to the logic high level.
If you look at the source termination scheme, where a resistor is placed in series with the driver, then you can see that the green trace has a similar rise time to the unterminated line. The signal and the reflections are attenuated by the series resistance and this has the effect of smoothing out the steps in the original rising edge. If you use split termination then you can see that the rise time is significantly sharper and the signal settles down to a steady state value very quickly compared to the other two schemes.
The other case to consider is when the driver is strong and has an output impedance that is low in comparison to the impedance of the trace.
In the example below we have repeated the three cases that we have above. This time we have a 12mA driver. In the unterminated case we have large initial overshoot at the receiver, which is reflected back down the line.
This situation continues until the line reaches a steady state. In this case the driver is strong but the line is long so the ringing is not as prolonged.
The source termination is shown as the green trace. The series termination has the effect of increasing the output impedance the driver. This lowers the initial amplitude of the signal into the transmission line. The ringing is on the line is eliminated.
When the split termination is used it can be seen that the termination has the effect of dampening the overshoot at the far end.
The examples provided can be used to show how performing IBIS simulations can help when evaluating the effects of different termination schemes.
Reflections on the line:
It can often happen that users measure the signal on the board and see reflections on the line that they cant explain. In this case the reflection can be present because the signal is not being observed at the end of the line.
Often the measurement is made at a via on the board or a test point that is located along the line. You can use an IBIS simulation of the trace and the drivers to mimic the measurement so that you can correlate with the hardware and also check what the signal is like at the pin or the die.
The following example shows how measuring a signal at a via on the board can give the impression that the signal quality is poor, when in fact it is not the case. IBIS simulations can be used in this case to correlate with hardware measurements.
In this example I have connected a small line to the via and loaded it with a cap. This is a good model of the probe and its effects. We can see that the signal looks poor at the via but it is fine at the receiver.
Xilinx SelectIO can use on die termination. This makes measurement in hardware very difficult as we can never measure the signal at the termination.
One common issue that comes up with this is that the package can cause reflections on the line. The termination is only present on the die, and even measuring very close to the die will cause the user to see the reflections due to the package.
In this case it is useful to look at the signal at the die in IBIS. For more information on Xilinx on-chip termination please see (Xilinx Answer 47499). For LVDS signals with DIFF_TERM enabled, please see (Xilinx Answer 40509).
IBIS simulators such as HyperLynx can be used to model PCB traces. The simulator allows the user to consider a variety of trace types.
One of the main advantages of this is to look at the effects of lengthening or shortening the trace. Adding a more accurate representation of the PCB trace you are dealing with will give a better simulation result.