AR# 50676


MIG v3.91 Virtex-6 DDR3/DDR2 - Design fails when "Add I/O Buffers" option is used in XST


The MIG Virtex-6 DDR3/DDR2 design explicitly instantiates I/O primitives into the HDL except for all of the address and control pins in the phy_control_io module.

Because the I/O Buffers are not instantiated for all of the signals, the IOSTANDARDS defined in the UCF are not binding properly to the port.


These failures only occur when the XST option "-iobuf" (Add I/O Buffers) is used.

This issue has been fixed with the 14.2 release for both the Verilog and VHDL designs. 



Answer Number 问答标题 问题版本 已解决问题的版本
50642 MIG Virtex-6 and Spartan-6 v3.92 - Release Notes and Known Issues for ISE Design Suite 14.3 N/A N/A
AR# 50676
日期 08/18/2014
状态 Active
Type 已知问题
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