AR# 50702


MIG 7 Series - VHDL designs fail simulation when using ISIM and Vivado Simulator


Version Found: v1.6
Version Resolved and other Known Issues: See (Xilinx Answer 45195).

The MIG 7 Series VHDL designs contain mixed VHDL and Verilog modules which cause a problem for ISIM and Vivado Simulator when attempting to pass down parameters across modules.


You might notice ISIM/Vivado Simulator exiting during compilation with erroneous error messages. This has been fixed for Vivado Simulator only.

Revision History
07/25/2012 - Initial release

AR# 50702
日期 02/08/2013
状态 Active
Type 已知问题
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