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AR# 50771

LogiCORE IP Video Deinterlacer v1.0/v2.00a - I cannot generate a core with 10-bit or 12-bit color depth


If I attempt to generate a Video Deinterlacer core and set color depth to 10 or 12, an error occurs during generation:

"The following error occurred : Failed to generate 'v_deinterlacer_v2_00_a'. Failed executing Tcl generator."

In the Core Generator Console, it shows another error:

"ERROR:sim - "tmp/_cg/_dbg/v_deinterlacer_v2_00_a/hdl/vhdl/deint_xsvi_out.vhd" Line 328: Left bound value <29> of slice is out of range [23:0] of array <m_axis_tdata>"


This issue is related to the bit width of the AXI-Stream interface. By default, it is set to 24, which is only for color depth 8-bit 4:4:4 video data (i.e., 8-bits x 3 color components = 24-bits).

If you are changing the color planes or the bit widths, you need to calculate the appropriate bit width needed to support that data width, then round up to the next 8-bit boundary when selecting the AXI4-Stream interface.

For color depth 10-bit or 12-bit, you should update the AXI4-Stream interfaces on page 4 to handle the larger bit widths; at least three times of color depth for 4:4:4 video data, and at least two times the color depth for 4:2:2 video data.

If color depth is 10-bit and the video data is 4:4:4, then you need at least a 30-bit AXI4-Stream interface. You should change the AXI-4 Stream interfaceto 32-bits. For instance, 10-bits *3 color components = 30-bits -> roundup to the next 8-bit boundary = 32-bit AXI4-Stream interface.

for a detailed list of LogiCORE IP Video Deinterlacer Release Notes and Known Issues, see (Xilinx Answer 41969).



Answer Number 问答标题 问题版本 已解决问题的版本
41969 LogiCORE IP Video Deinterlacer - Release Notes and Known Issues N/A N/A
AR# 50771
日期 01/16/2013
状态 Active
Type 综合文章
  • FPGA Device Families
  • Video Deinterlacer