AR# 50808


LogiCORE IP Ten Gigabit Ethernet PCS/PMA (10GBASE-R/10GBASE-KR) v2.4 - Updates needed to reset/initialization logic for cable pull/ RX data input not present


When targeting 7 series FPGAs with the Ten Gigabit Ethernet PCS/PMA (10GBASE-R/10GBASE-KR) v2.4 core, updates are needed to the reset/initialization logic for the core and GT, if the core will be operating under the following conditions:

A system where there could be a cable unplug, a link partner reset, or another cause for no RX data to be present at the serial input to the GT.


The updated reset/initialization logic is currently being tested and this answer record will be updated once it is available. 

To check on the status, please open a WebCase with Xilinx Technical Support:

AR# 50808
日期 11/06/2014
状态 Active
Type 综合文章
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