UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 50885

Logicore IP Aurora 64B66B v7.2 - Compile error while using the script implement_synplify.bat/implement_synplify.sh to implement the example design

描述

If implement_synplify.bat/implement_synplify.sh is used to implement the example design, the following error will occur:

Reference to undefined module aurora_64b66b_dup_core, the "aurora_64b66b_dup_core" module is not found in the run

This Answer recordhelps to resolve this error

解决方案

The compilation of <component name>_core.v[hd] file is missing insynplify.prj file and is causing compilation error.
Add the following line to the synplify.prj file
Verilog:
add_file -verilog "../../<component name>_core.v"
VHDL:
add_file -vhdl "../../<component name>_core.vhd"
Revision History:
1.0 - Initial release
AR# 50885
日期 11/28/2012
状态 Active
Type 综合文章
Tools
  • ISE Design Suite - 14.2
IP
  • Aurora 64B/66B
的页面