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14.1 EDK/SDK - Are there any ECC limitations on the Zynq device DDRx controller?
Are there any ECC limitations on the Zynq device DDRx controller?
ECC needs 26 bits of DRAM width. How this is allocated is up to the user. However, the most efficient means would probably be 1x 32-bit device.
All of 1x32, 2x16, or 4X8 would work fine.