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AR# 50898

14.1 EDK/SDK - Are there any ECC limitations on the Zynq device DDRx controller?

描述

Are there any ECC limitations on the Zynq device DDRx controller?

解决方案

ECC needs 26 bits of DRAM width. How this is allocated is up to the user. However, the most efficient means would probably be 1x 32-bit device.

All of 1x32, 2x16, or 4X8 would work fine.

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
52540 Zynq-7000 AP SoC - Frequently Asked Questions N/A N/A
AR# 50898
日期 02/04/2013
状态 Active
Type 综合文章
Tools
  • EDK - 14.1
的页面