解决方案
Technical Support
To obtain technical support, create a WebCase at www.xilinx.com/support, Questions are routed to a team with expertise using this product.
Xilinx provides technical support for use of this product when used according to the guidelines described in the core documentation, and cannot guarantee timing, functionality, or support of this product for designs that do not follow specified guidelines
LogiCORE IP Distributed Memory Generator v7.2
New Features
ISE
- ISE 14.2 software support
- Example test bench support
Vivado
- 2012.2 software support
- Example test bench support
- XSIM Simulator support
Supported Devices
ISE
The following device families are supported by the core for this release.
All 7 Series devices
Zynq-7000 devices
All Virtex-6 devices
All Spartan-6 devices
All Virtex-5 devices
All Spartan-3 devices
All Virtex-4 devices
Vivado
All 7 Series devices
Zynq-7000 devices
Resolved IssuesISE
- N/A
Vivado
- N/A
Known Issues ISE
There are not known issues for v7.2 of this core at time of release:
Vivado
LogiCORE IP Distributed Memory Generator v7.1
New Features
ISE
- ISE 14.1 software support
- Defense Grade Virtex-7Q, Kintex-7Q, Artix-7Q and Zynq-Q, Defense Grade Lower Power
- Kintex-7QL and Artix-7QL, and Automotive Zynq device support
Vivado
- 2012.1 software support
- Defense Grade Virtex-7Q, Kintex-7Q, Artix-7Q and Zynq-Q, Defense Grade Lower Power Kintex-7QL and Artix-7QL, and Automotive Zynq device support
Supported Devices
ISE
The following device families are supported by the core for this release.
All 7 Series devices
Zynq-7000 devices
All Virtex-6 devices
All Spartan-6 devices
All Virtex-5 devices
All Spartan-3 devices
All Virtex-4 devices
Vivado
All 7 Series devices
Zynq-7000 devices
Resolved Issues
-N/A
Known Issues
There are no known issues for v7.1 of this core at time of release
LogiCORE IP Distributed Memory Generator v6.3
New Features
- ISE 13.4 software support
Resolved Issues
The following issues are resolved in v6.3:
- The Distributed Memory Generator IP GUI is not showing the Simple DualPort Memory option for the use.
Version Fixed: v6.3
- CR 620314
Known Issues
There are no known issues for v6.3 of this core at time of release
LogiCORE IP Distributed Memory Generator v6.2
New Features
-ISE 13.2 software support
-Kintex-7L, Virtex-7L, Artix-7 and Zynq device support
Resolved Issues
When a large Distributed Memory Generator IP is generated, the CORE Generator runs out of memory and fails to generate.
Known Issues
None
LogiCORE IP Distributed Memory Generator v4.2
New Features - ISE 11.3 software support
- Virtex-6 Lower Power and Virtex-6 HXT device support
- Spartan-3A/-3A DSP Automotive device support
Resolved Issues - Default Data option is unavailable in the core GUI for Spartan-6 devices.
- Version fixed: 4.2
- CR 522888
- AR 32753
- In Distributed Memory Generator VHDL behavioral model, DOUT is undefined initially until a read occurs
- Version fixed: 4.2
- CR 523629
- AR 32816
Known Issues(Xilinx Answer 21393) - When a large Distributed Memory Generator IP is generated, CORE Generator runs out of memory and fails to generate - CR 431917
LogiCORE IP Distributed Memory Generator v4.1.1
New Features
- ISE 11.2 software support
- Virtex-6 and Spartan-6 device support
Resolved Issues
- Incorrect address bus and select lines in Figures 4 and 6 in the Distributed Memory Generator data sheet
- CR # 511558
Known Issues
- Virtex-6 and Spartan-6 solutions are pending hardware validation
(Xilinx Answer 21393) - When a large Distributed Memory Generator IP is generated, CORE Generator runs out of memory and fails to generate - CR 431917
(Xilinx Answer 32753) - Default Data option is unavailable in the core GUI for Spartan-6 devices - CR 522888
(Xilinx Answer 32816) - VHDL behavioural model drives unknown value on DOUT for Spartan-6 devices - CR 523629
LogiCORE IP Distributed Memory Generator v4.1
New Features
- ISE 11.1 software support
Resolved Issues
None
Known Issues
(Xilinx Answer 21393) - When a large Distributed Memory Generator IP is generated, CORE Generator runs out of memory and fails to generate - CR 431917
LogiCORE IP Distributed Memory Generator v3.4
New Features
-ISE 10.1 software support
Resolved Issues
(Xilinx Answer 25360) - DPRA Reg is clocked by CLK unless output registers are used. DPRA Reg should be clocked by QDPO_CLK regardless of whether output registers are implemented - CR 440076
(Xilinx Answer 25361) - Figure 6 of the Distributed RAM data sheet (DS322) shows incorrect clocking for QDPO_CE and QSPO_CE - CR 440140
Known Issues
(Xilinx Answer 21393) - When a large Distributed Memory Generator IP is generated, CORE Generator runs out of memory and fails to generate - CR 431917
LogiCORE IP Distributed Memory Generator v3.3.1
For installation instructions for IP Update #1 and design tools requirements, see (Xilinx Answer 24307).
For installation instructions for IP Update #2 and design tools requirements, see (Xilinx Answer 24628).
Installing IP Update # 2 upgrades the core to "Rev 1" status and enables Spartan3A DSP support.
All known issues mentioned in this Answer Record is still applicable.
New Features
No new features in this release.
Resolved Issues
CR 415385 - Dist_Mem_Gen failed when Width = 1 and Family = Virtex4.
CR 326740 - Excessive register duplication in distributed memory synthesis.
(Xilinx Answer 24617) - Simulation warning "MIF file size does not match memory size" when MIF file is used.
Known Issues
(Xilinx Answer 21393) - When a large Distributed Memory Generator IP is generated, CORE Generator runs out of memory and fails to generate.
LogiCORE IP Distributed Memory Generator v3.3
For installation instructions for IP Update #1 and design tools requirements, see (Xilinx Answer 24307).
For installation instructions for IP Update #2 and design tools requirements, see (Xilinx Answer 24628).
Installing IP Update # 2 upgrades the core to "Rev 1" status and enables Spartan3A DSP support.
All known issues mentioned in this Answer Record is still applicable.
New Features
No new features in this release.
Resolved Issues
CR 415385 - Dist_Mem_Gen failed when Width = 1 and Family = Virtex4.
CR 326740 - Excessive register duplication in distributed memory synthesis.
(Xilinx Answer 24617) - Simulation warning "MIF file size does not match memory size" when MIF file is used.
Known Issues(Xilinx Answer 21393) - When a large Distributed Memory Generator IP is generated, CORE Generator runs out of memory and fails to generate.
LogiCORE IP Distributed Memory Generator v3.2
New Features
- Added Spartan-3A support
- Added pipelined outputs
Resolved Issues
None
Known Issues(Xilinx Answer 21393) - When a large Distributed Memory Generator IP is generated, CORE Generator runs out of memory and fails to generate
LogiCORE IP Distributed Memory Generator v3.1
New Features
Support added for Virtex-5
Support added for ISE 8.2i design tools
Resolved Issues
CR 225505: COE parser does not recognize newline as whitespace has been fixed
CR 230095: Figure 6 in data sheet has a wiring error that has been corrected
Known Issues(Xilinx Answer 21393) When a large Distributed Memory Generator IP is generated, CORE Generator runs out of memory and fails to generate.