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Xilinx SelectIO Solution Center

The SelectIO Solution Center is available to address all questions related to SelectIO.

Whether you are starting a new design with SelectIO or troubleshooting a problem, use the SelectIO solution center to guide you to the right information.

设计助手

Xilinx SelectIO Solution Center - Design Assistant

The Design Assistant will walk you through the recommended design flow for designing with Xilinx SelectIO pins, while debugging commonly encountered issues. 

The Design Assistant will not only provide useful design and troubleshoot information, but also point you to the exact documentation you need to read to help you design efficiently with Xilinx SelectIO.

Note: This article is part of the Xilinx SelectIO Solution Center (Xilinx Answer 50924).

The Xilinx SelectIO Solution Center is available to address all questions related to SelectIO.

Whether you are starting a new design or troubleshooting a problem, use the SelectIO Solution Center to guide you to the right information.


The SelectIO Design Assistant is broken into sections (though they overlap). Please choose the section most related to your question or query.

This will ensure that the SelectIO Design Assistant points you to the information you need to continually move forward with your design.


IO Specifications and Performance:

(Xilinx Answer 47284) addresses questions on factors affecting performance:

  • Single-ended, Differential, and Pseudo-differential (Complimentary single-ended) I/O standards
  • SelectIO performance-related specifications provided in Xilinx data sheets

Termination and SelectIO:

(Xilinx Answer 47225) addresses questions on terminating transmission lines:

  • Basics of transmission lines
  • The types of termination depending on the I/O standard
  • How to setup optional internal termination in a design
  • Debugging issues with internal terminations


Board Level Debug

(Xilinx Answer 50537) addresses questions on debugging signal integrity issues:

  • SSO/SSN - Simultaneously Switching Output/Noise
  • Debugging issues with reflections or ringing
  • Debugging issues with data eyes
  • Debugging issues with signals not crossing expected thresholds


IO settings in the Xilinx Tools

(Xilinx Answer 47368) addresses questions on IOSTANDARDs

  • Types of IOSTANDARDs
  • Interfacing with Various IOSTANDARDs


Signal Integrity Simulations

(Xilinx Answer 50644) addresses questions on IBIS Models & Simulation

  • What information is contained in a IBIS models
  • Known issues with Xilinx IBIS models


IO Electrical Reliability

(Xilinx Answer 51834) addresses questions on the following:

  • Over driving I/Os - undershoot and overshoot
  • Hot swapping/plugging
  • Power sequencing and the I/O state during powering and configuration

技术文档

Xilinx SelectIO Solution Center - Documentation

Please refer to the following documentation when using SelectIO

Note: This article is part of the Xilinx SelectIO Solution Center (Xilinx Answer 50924).

The Xilinx SelectIO Solution Center is available to address all questions related to SelectIO.

Whether you are starting a new design or troubleshooting a problem, use the SelectIO Solution Center to guide you to the right information.


The two main sources of documentation for SelectIO are the DC and Switching Characteristics Data Sheet, and the SelectIO User Guide (note that for older devices, SelectIO was a chapter in the family User Guide).

The DC and Switching Characteristics Data Sheet contains tables of Input and Output Voltage Thresholds.

The SelectIO User Guides are invaluable for SelectIO information including:

  • Details of all of the supported IOSTANDARDs
  • The expected termination for each IOSTANDARD
  • The voltage requirements (Vcco and Vref)
  • Details on which attributes are supported for each IOSTANDARD
  • Details on how to combine IOSTANDARDs in a bank
  • DCI and DCI cascading information


Zynq UltraScale+ MPSoC SelectIO Documentation:

(UG571)UltraScale Architecture SelectIO User Guide
(UG1085)Zynq UltraScale+ MPSoC TRM (There are descriptions for all the MIO peripheral signaling)
(DS925)Zynq UltraScale+ MPSoC DC and AC Switching Characteristics Data Sheet

UltraScale+ SelectIO Documentation:

(UG571)UltraScale Architecture SelectIO User Guide
(DS922)Kintex UltraScale+ DC and AC Switching Characteristics Data Sheet
(DS923)Virtex UltraScale+ DC and AC Switching Characteristics Data Sheet

UltraScale SelectIO Documentation:

(UG571)UltraScale Architecture SelectIO User Guide
(DS892)Kintex UltraScale DC and AC Switching Characteristics Data Sheet
(DS893)Virtex UltraScale DC and AC Switching Characteristics Data Sheet

Zynq-7000 AP SoC SelectIO Documentation:

(UG471)7 Series SelectIO User Guide
(UG585)Zynq TRM (There are descriptions for all the MIO peripheral signaling)
(DS187)ZC7007S/7012S/7014S/7010/7015/7020 DC and AC Switching Characteristics Data Sheet
(DS191)ZC7030/7030/7045/7100 DC and AC Switching Characteristics Data Sheet

7 Series SelectIO Documentation:

(UG471)7 Series SelectIO User Guide
(DS181)Artix-7 DC and AC Switching Characteristics Data Sheet
(DS182)Kintex-7 DC and AC Switching Characteristics Data Sheet
(DS183)Virtex-7 DC and AC Switching Characteristics Data Sheet

Virtex-6 SelectIO Documentation:

(UG361)Virtex-6 SelectIO User Guide
(DS186)Virtex-6 DC and AC Switching Characteristics Data Sheet

Spartan-6 SelectIO Documentation:

(UG381)Spartan-6 SelectIO User Guide
(DS162)Spartan-6 DC and AC Switching Characteristics Data Sheet

Virtex-5 SelectIO Documentation:

(UG190)Virtex-5 Family User Guide
(DS202)Spartan-6 DC and AC Switching Characteristics Data Sheet

Spartan-3 SelectIO Documentation:

(UG331)Spartan-3 Family User Guide
(DS099)Spartan-3 DC and AC Switching Characteristics Data Sheet
(DS529)Spartan-3A DC and AC Switching Characteristics Data Sheet
(DS706)Spartan-3A Extended DC and AC Switching Characteristics Data Sheet
(DS557)Spartan-3AN DC and AC Switching Characteristics Data Sheet
(DS312)Spartan-3E DC and AC Switching Characteristics Data Sheet

设计咨询

Xilinx SelectIO 解决方案中心 — 设计咨询

下文列出了与 SelectIO 有关的 Xilinx 当前设计咨询。

注意:本文是 (Xilinx 答复 50924) Xilinx SelectIO 解决方案中心的一部分。Xilinx SelectIO 解决方案中心可解决所有与 SelectIO 相关的问题。

无论您是要启动新设计还是要调试问题,请访问 SelectIO 解决方案中心来指导您获取相应的信息。


设计咨询列表


Zynq UltraScale+ MPSoC

(Xilinx 答复 66944)有关 Zynq UltraScale+ MPSoC 的设计咨询 - 自 2016 年 4 月 5 日起,更新与 Xilinx.com 相关的封装管脚 


UltraScale


(Xilinx 答复 65998)设计咨询 — 系统监控器和 PCI Express:I2C_SDA、I2C_SCL、PERSTN0 或 PERSTN1 I/O 引脚的引脚电压低于预期电压 
(Xilinx 答复 62483)MIG UltraScale 设计咨询(所有存储器类型)— VRP 引脚及 DCI 级联要求

Artix-7 

(Xilinx 答复 58162)Artix-7 FPGA 焊线封装器件的设计咨询 - 当使用 GTP 收发器时的 SelectIO 禁止引脚列表 

Spartan-6 

(Xilinx 答复 35237)Spartan-6 FPGA GTP收发器设计咨询 – GPIO(用户输入输出管脚)到GTP的串扰/SSO(同时开关输出)准则
(Xilinx 答复 40818) - Spartan-6 INTERM_XX 未能在 Spartan-6 FPGA 输入的 BitGen 中正确开启


注册查看设计咨询及新出现的问题:

实时查看 Xilinx 设计咨询并了解新问题的最佳途径是通过您的 Xilinx.com 账户进行注册,获得相关通知。

如欲了解详细注册指南,请查看以下答复记录:

(Xilinx 答复 18683)


Answer Number 问答标题 问题版本 已解决问题的版本
40818 Spartan-6 SelectIO 设计咨询 — INTERM_XX 未能在 Spartan-6 FPGA 输入的 BitGen 中正确开启 N/A N/A
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