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AR# 50926

Xilinx SelectIO Solution Center - Design Assistant


The Design Assistant will walk you through the recommended design flow for designing with Xilinx SelectIO pins, while debugging commonly encountered issues. 

The Design Assistant will not only provide useful design and troubleshoot information, but also point you to the exact documentation you need to read to help you design efficiently with Xilinx SelectIO.

Note: This article is part of the Xilinx SelectIO Solution Center (Xilinx Answer 50924).

The Xilinx SelectIO Solution Center is available to address all questions related to SelectIO.

Whether you are starting a new design or troubleshooting a problem, use the SelectIO Solution Center to guide you to the right information.


The SelectIO Design Assistant is broken into sections (though they overlap). Please choose the section most related to your question or query.

This will ensure that the SelectIO Design Assistant points you to the information you need to continually move forward with your design.

IO Specifications and Performance:

(Xilinx Answer 47284) addresses questions on factors affecting performance:

  • Single-ended, Differential, and Pseudo-differential (Complimentary single-ended) I/O standards
  • SelectIO performance-related specifications provided in Xilinx data sheets

Termination and SelectIO:

(Xilinx Answer 47225) addresses questions on terminating transmission lines:

  • Basics of transmission lines
  • The types of termination depending on the I/O standard
  • How to setup optional internal termination in a design
  • Debugging issues with internal terminations

Board Level Debug

(Xilinx Answer 50537) addresses questions on debugging signal integrity issues:

  • SSO/SSN - Simultaneously Switching Output/Noise
  • Debugging issues with reflections or ringing
  • Debugging issues with data eyes
  • Debugging issues with signals not crossing expected thresholds

IO settings in the Xilinx Tools

(Xilinx Answer 47368) addresses questions on IOSTANDARDs

  • Types of IOSTANDARDs
  • Interfacing with Various IOSTANDARDs

Signal Integrity Simulations

(Xilinx Answer 50644) addresses questions on IBIS Models & Simulation

  • What information is contained in a IBIS models
  • Known issues with Xilinx IBIS models

IO Electrical Reliability

(Xilinx Answer 51834) addresses questions on the following:

  • Over driving I/Os - undershoot and overshoot
  • Hot swapping/plugging
  • Power sequencing and the I/O state during powering and configuration



Answer Number 问答标题 问题版本 已解决问题的版本
50924 Xilinx SelectIO Solution Center N/A N/A


AR# 50926
日期 06/02/2017
状态 Active
Type 解决方案中心
  • FPGA Device Families