AR# 50929

AutoESL - Zynq SoC Design Example with AXI-DMA Core for Data Transfer

描述

This answer record contains the Zynq SoC design example with AXI-DMA core for data transfer.

解决方案

The documentation and design file (AutESL_Zynq_Training_Labs.pdf, and autoesl_zynq_training_labs.zip) that are linked at the end of this answer record provide the following exercises:

  • Create a basic Zynq SoC system
  • Instantiate an AutoESL generated block in a Zynq SoC system
  • Debug the communication between AutoESL generated IP and ARM
  • Connect two AutoESL IPs using AXI4-streaming
  • Use the AXI-DMA core for data transfers to external memory from AutoESL IP

附件

文件名 文件大小 File Type
Microsoft Word - ZYNQ and AutoESL Training Labs 4 MB PDF
autoesl_zynq_training_labs.zip 45 KB ZIP

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
47431 Xilinx Vivado HLS Solution Center - Design Assistant N/A N/A
AR# 50929
日期 05/17/2018
状态 Active
Type 解决方案中心
Tools