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AutoESL - Zynq SoC Design Example with AXI-DMA Core for Data Transfer
This answer record contains the Zynq SoC design example with AXI-DMA core for data transfer.
The documentation and design file (AutESL_Zynq_Training_Labs.pdf, and autoesl_zynq_training_labs.zip) that are linked at the end of this answer record provide the following exercises:
- Create a basic Zynq SoC system
- Instantiate an AutoESL generated block in a Zynq SoC system
- Debug the communication between AutoESL generated IP and ARM
- Connect two AutoESL IPs using AXI4-streaming
- Use the AXI-DMA core for data transfers to external memory from AutoESL IP