解决方案
To use the High Range I/O for Virtex-7 and Kintex-7 SPI-4.2 cores:
1. Update any applicable IOSTANDARD generics on I/O buffer instantiations in the example design from "LVDS" to "LVDS_25."
For the example design, these are located in <core_name>_l4_src_clk.v[hd], <core_name>_pl4_snk_clk.v[hd], and <core_name>_top.v[hd].
2. Add the following to the XDC file:
For the Source Core:
set_property IOSTANDARD LVDS_25 [get_cells <core_instant_name>/U0/pl4_src_top/*pl4_src_top/io0/src_ddr*/*ddr*_buf]
set_property IOSTANDARD LVDS_25 [get_cells <core_instant_name>/U0/pl4_src_top/*pl4_src_top/io0/src_ctl*/*ddr*_buf]
set_property IOSTANDARD LVDS_25 [get_cells <core_instant_name>/U0/pl4_src_top/*pl4_src_top/io0/TDClk_buf_v7.src_buf]
For the Dynamic Sink Core:
set_property IOSTANDARD LVDS_25 [get_cells <core_instant_name>/U0/pl4_snk_top/*pl4_snk_top/io0/*dpa/dpa_top0/*DATAPAIR*/*BUFIN*.INBUF*]
set_property IOSTANDARD LVDS_25 [get_cells <core_instant_name>/U0/pl4_snk_top/*pl4_snk_top/io0/*dpa/dpa_top0/*CTLPAIR*/*BUFIN*.INBUF*]
For the Static Sink Core:
set_property IOSTANDARD LVDS_25 [get_cells <core_instant_name>/U0/pl4_snk_top/*pl4_snk_top/io0/StaticAlign.buffer_data/*BUFIN*]
3. Update any pin LOC constraints or other placement constraints as necessary to target High Range I/O banks.