AR# 50962

描述

解决方案

The SEM IP v3.2 used an XDCconstraint 'set_max_delay' to constrain timing between the FRAME_ECC primitive start points and various timing end points. This constraint was written incorrectly, which resulted in unconstrained timing paths.

These constraints have been corrected forv3.3 of the core. Use the new set_max_delay constraints, as generated in the IP's example XDC constraints file.

Below is an example of the syntax, but the actual numbers will be based on the user's specified clock frequency. For a 70 MHz clock, the set_max_delay constraints would be:

• set_max_delay 11.285 -from [get_pins example_cfg/example_frame_ecc/*] -quiet
• set_max_delay 28.57 -from [get_pins example_cfg/example_frame_ecc/*] -to [all_outputs] -quiet

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