UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 50962

Soft Error Mitigation Core v3.2 - The XDC set_max_delay constraints are incorrect

描述

The Soft Error Mitigation (SEM) IP v3.2 used an XDC constraint 'set_max_delay'. The constraint was incorrect, resulting in unconstrained paths. This issue was corrected in the SEM IP v3.3, released with Vivado 2012.2.

解决方案

The SEM IP v3.2 used an XDCconstraint 'set_max_delay' to constrain timing between the FRAME_ECC primitive start points and various timing end points. This constraint was written incorrectly, which resulted in unconstrained timing paths.

These constraints have been corrected forv3.3 of the core. Use the new set_max_delay constraints, as generated in the IP's example XDC constraints file.

Below is an example of the syntax, but the actual numbers will be based on the user's specified clock frequency. For a 70 MHz clock, the set_max_delay constraints would be:

  • set_max_delay 11.285 -from [get_pins example_cfg/example_frame_ecc/*] -quiet
  • set_max_delay 28.57 -from [get_pins example_cfg/example_frame_ecc/*] -to [all_outputs] -quiet

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
44541 Soft Error Mitigation Controller - Release Notes and Known Issues for v1.1 to v3.4 N/A N/A
AR# 50962
日期 02/07/2013
状态 Active
Type 已知问题
Tools
  • Vivado
IP
  • Soft Error Mitigation
的页面