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AR# 51019

2012.2 Vivado HLS - Known Issues


This answer record lists known issues and limitations for 2012.2 Vivado HLS.


Coding Style
- Multiple inheritance of virtual functions is not supported.
-On 64-bit operation systems, "long' data types might cause a simulation mismatch. The "long long" data type is recommended for 64-bit integers.

Directive/Pragma Usage
- Design level handshake signals are not added if there is a valid output on every cycle. If interface mode ap_ctrl_hs is selected, which is also the default, it is expected that design level handshakes such as ap_start or ap_done, are added to the design. However, if the design is pipelined with II=1, such that there is valid output on every clock cycle, the design level handshakes will be optimized in the final RTL. This issue will be resolved in a future release.
- Complete array partitioning on multiple variables indexed array accesses may lead to long runtime and excessive memory usage.
Array[x] = y;
Array[x+1] = y+1;
Array[x+N] = y+N;
#pragma AP array partition variable=Array
- Pragmas on C__ class objects such as ap_int, ap_fixed variables, require additional ampersand &. No such requirement for tcl directives.
ap_int<N>x = y*z;
#pragma AP resource core=PipeMul2S variable=&x
- The array streaming directive cannot configure the FIFO depth for scalar variables in dataflow.
Void DUT(Type_M in_data[N], Type_M out_data[N})
Type_M mem[N]; // Can configure depth with array streaming if
// this array is converted into FIFO.
bool flag; // Cannot configure depth for this scalar variable.
//bool flag[1]; // Workaround of using single-element array.
read_data(in_data, mem, &flag);
write_data(out_data, memo, flag);

RTL Co-Simulation
- Segmentation fault in C simulation of the pre-synthesis test bench and design under test (DUT) or test bench in post-0synthesis co-simulation. This can occur if the code contains array which are large, as these require a large stack space. Two potential work-arounds are available:
- Using a static qualifier will move the arrays out of stack.
- The shell command, ulimit -s, can also be used to increase stack size.
- Using the C compilation flag -O2 to optimize the run time performance during C simulation might cause the RTL simulation (a co-simulation of the C test bench and RTL) to fail.
- To optimize the run time of the C simulation, especially when using floating point types, remove any -O2 used with the add_files -cflag option.



Answer Number 问答标题 问题版本 已解决问题的版本
47397 Vivado Design Suite 2012 - Known Issues N/A N/A
47429 Xilinx Vivado HLS Solution Center - Top Issues N/A N/A
AR# 51019
创建日期 07/26/2012
Last Updated 07/26/2012
状态 Active
Type 已知问题
  • Vivado - 2012.2