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AR# 5103

8.1i Timing/Constraints - A confusing constraint header is displayed when "4X" is invoked with CLKDLL

Description

In Virtex devices and derivatives, it is possible to place two CLKDLLs in a row to achieve a 4X multiplication of the input clock signal. When a constraint is placed on the input of the CLKDLL, TRCE/Timing Analyzer will create a new constraint for each of the outputs.

After going through the second DLL 2X tap, the constraint header quotes the original constraint and says that it is multiplying by 2; it then displays the new constraint correctly multiplied by 4. The correct constraint is created, but the text in the constraint header is incorrect and can be confusing.

解决方案

This issue will be resolved in a future software release.

AR# 5103
创建日期 08/21/2007
Last Updated 01/18/2010
状态 Archive
Type 综合文章