In Virtex devices and derivatives, it is possible to place two CLKDLLs in a row to achieve a 4X multiplication of the input clock signal. When a constraint is placed on the input of the CLKDLL, TRCE/Timing Analyzer will create a new constraint for each of the outputs.
After going through the second DLL 2X tap, the constraint header quotes the original constraint and says that it is multiplying by 2; it then displays the new constraint correctly multiplied by 4. The correct constraint is created, but the text in the constraint header is incorrect and can be confusing.
This issue will be resolved in a future software release.