We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 5104

9.1i PAR - What is an "antenna" in the context of the Place and Route program (PAR)?


What is an "antenna" in the context of the PAR place-and-route program?


An antenna is a routing stub that has only one connection, which is to say that it has a source, but does not terminate at a pin. PAR should not leave any antennas in your placed and routed design. If you see antenna errors in your design after running PAR, this is a problem that needs to be fixed.

If you edited your design using FPGA Editor, antennas may appear if one of the signals was not routed completely.

Antennas may or may not affect your design, depending on whether or not the signal in question makes all the connections it actually needs. Also, antennas can have an unfavorable effect on noise immunity if the signal in question switches at a high frequency.



Answer Number 问答标题 问题版本 已解决问题的版本
54795 VIVADO IMPLEMENTATION - How can I fix Partial Antenna problems, [Drc 23-20] N/A N/A
AR# 5104
日期 03/07/2013
状态 Active
Type 综合文章