AR# 51047

7 Series FPGA GTX Transceivers - Recommended PLL settings for various protocols

描述

This answer record specifies the recommended PLL settings and dividers to use in 7 series FPGA GTX transceivers for the various protocols. This information will be added to the next revision (v1.6) of the 7 Series FPGAs GTX/GTH Transceivers User Guide (UG476).

解决方案

Standard	Line Rate	Internal Data Width	PLL Frequency	REFCLK Frequency	Using Typical REFCLK Frequency
	[Gb/s]	[16b/20b/32b/40b]	[GHz]	[MHz]	Using Typical REFCLK Frequency
				Typical	N1	N2	D	M
XAUI	3.125	20b	3.125	156.25	5	4	2	1
GigE	1.25	20b	2.5	125	5	4	4	1
PCIe Optimal Jitter	5	20b	2.5	250	5	2	1	1
	2.5	20b	2.5	250	5	2	2	1
	5	20b	2.5	125	5	4	1	1
	2.5	20b	2.5	125	5	4	2	1
PCIe 100 MHz REFCLK	5	20b	2.5	100	5	5	1	1
PCIe 100 MHz REFCLK	2.5	20b	2.5	100	5	5	2	1
CPRI 1-4X (Multi-Rate)	2.4576	20b	2.4576	122.88	5	4	2	1
	1.2288	20b	2.4576	122.88	5	4	4	1
	0.6144	20b	2.4576	122.88	5	4	8	1
CPRI 1-10X (Multi-Rate)	3.072	20b	3.072	122.88	5	5	2	1
	2.4576	20b	2.4576	122.88	5	4	2	1
	1.2288	20b	2.4576	122.88	5	4	4	1
	0.6144	20b	2.4576	122.88	5	4	8	1
CEI 6.25	6.25	20b	3.125	390.625	4	2	1	1

Standard	Line Rate	Internal Data Width	PLL Frequency	QPLL	REFCLK Frequency	Using Typical REFCLK Frequency
	[Gb/s]	[16b/20b/32b/40b]	[GHz]	[Upper/Lower Band]	[MHz]	Using Typical REFCLK Frequency
					Typical	N (QPLL_FBDIV, QPLL_FBDIV_RATIO)	RXOUT_DIV (D)	TXOUT_DIV (D)	M (QPLL_REFCLK_DIV)
PCIe Gen3	8	32b	8	Lower	100	80	1	1	1
CEI 6.25	6.25	20b	6.25	Lower	390.625	16	1	1	1
CEI 6.25	6.25	20b	6.25	Lower	156.25	40	1	1	1
CEI 11	9.95	32b	9.95	Upper	155.46875	64	1	1	1
CEI 11	11.1	32b	11.1	Upper	173.4375	64	1	1	1
SFP+ (SFF-8431,SFI)	9.8304*	32b	9.8304	Upper	122.88	80	1	1	1
	9.95328	32b	9.95328	Upper	155.52	64	1	1	1
	10.3125	32b	10.3125	Upper	156.25	66	1	1	1
	10.5187	32b	10.5187	Upper	164.355	64	1	1	1
	11.1	32b	11.1	Upper	173.4375	64	1	1	1

NOTE: * Line rate used for CPRI over SFP+ applications.

本答复记录是否对您有帮助？

AR# 51047
日期	11/28/2012
状态	Active
Type	综合文章
器件	Kintex-7 Virtex-7

的页面