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AR# 51063

14.1 Zynq-7000 - Why is QSPI programming not working when the feedback clock is used?

Description

When programming or operating a QSPI device with a clock frequency greater than FQSPICLK2 (see DS187), MIO[8] (qspi_sclk_fb_out) can only be floated or connected to a pull-up/pull-down resistor on the PCB, and Quad-SPI external loopback must be enabled.

Check that the MIO[8] pin is not connected to any additional resistive or capacitive loads other than what is stated in the Zynq TRM when using the QSPI with the Feedback Clock mode enabled.

解决方案

To program QSPI reliably with a clock that is greater than FQSPICLK2:

  • Ensure that the MIO[8] (qspi_sclk_fb_out) is floated or connected to a pull-up/pull-down resistor on the PCB, and that the Quad-SPI external loopback is be enabled. MIO[8] must be free of any additional loading.

To program QSPI reliably with a QSPI Clock that is less than FQSPICLK2:

  • Ensure that the operating frequency (QSPI interface clock) is lower than FQSPICLK2 (see DS187).
  • Make sure QSPI external loopback is disabled (see qspi.LPBK_DLY_ADJ register in the Zynq TRM).
  • Disabling the feedback mode allows MIO[8] to be used with additional loading.

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
52540 Zynq-7000 AP SoC - Frequently Asked Questions N/A N/A

相关答复记录

AR# 51063
创建日期 09/05/2012
Last Updated 10/24/2012
状态 Active
Type 已知问题
器件
  • Zynq-7000
Tools
  • EDK - 14.1