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AR# 51100

Timing - OFFSET contraints on the FCLK are being ignored in Zynq SoC designs

Description

OFFSET constraints on the FCLK are being ignored in Zynq SoC designs. 

A warning similar to the following displays on the console:

WARNING: ConstraintSystem:168 - Constraint <OFFSET = OUT 10 ns AFTER "system_i/processing_system7_0_FCLK_CLK_0<0>";> [system_top.ucf(5)]:
This constraint will be ignored because NET system_i/processing_system7_0_FCLK_CLK_0<0>"could not be found or was not connected to a PAD."

How can I work around this issue?

解决方案

This is a known issue of ISE Timing Analyzer. 

For inputs/outputs clocked off one of the PS clocks, the ISE timing engine is unable to recognize the clock as an input pad. 

So Offset constraints do not work here.

To work around this issue, the same analysis will have to be done manually. 

A set of FROM TO constraints will have to be given in the UCF. 

Follow the instructions below to set up the FROM-TO constraints and do the manual analysis.


Workaround for OFFSET IN constraint

1. Setup analysis

The OFFSET IN Setup Slack equation is:
Setup Slack = setup requirement - (data path - clock path - clock arrival + uncertainty))

In order for setup slack >=0, data path delay should not exceed N = (setup requirement + clock path + clock arrival - uncertainty). So N is the requirement value for the FROM-TO constraint.

  • setup requirement : this is the OFFSET IN value
  • clock path : in setup analysis, minimum clock path delay needs to be used. This delay can be seen by doing user-specified endpoint analysis, setting source to the clock input pad and destination to input FF. The minimum clock path delay is given in Hold paths under this path filter analysis. For more information please see (Xilinx Answer 2742)
  • clock arrival : clock arrival is determined by whether the input clock is phase shifted
  • uncertainty : The clock uncertainty can be estimated from timing analyzer if the fclk clocks a synchronous path (e.g., FF to FF), TA will give an uncertainty which you can plug into the above equation.

Then a FROM-TO constraint should be used between the input pad and the input register.

net <input_pad_name> TNM = input_pad_grp;
inst <input_register_name> TNM = input_reg_grp;
TIMESPEC TS_offset_in = FROM input_pad_grp TO input_reg_grp N ns;


2. Hold Analysis

The OFFSET IN Hold Slack equation is like this:
Hold Slack = hold requirement - (clock path + clock arrival + uncertainty - data path)

In order for hold slack >=0, data path delay should not be less than M = (clock path + clock arrival + uncertainty - hold requirement)


  • hold requirement : this is (VALID value - OFFSET IN value)
  • clock path : in hold analysis, maximum clock path delay is used. This delay can be seen by doing user-specified endpoint analysis, setting source to the clock input pad and destination to input FF. The maximum clock path delay is given in Setup paths under this path filter analysis. For more information please see (Xilinx Answer 2742)
  • clock arrival : clock arrival is determined by whether the input clock is phase shifted
  • uncertainty : The clock uncertainty can be estimated from the timing analyzer if the fclk clocks a synchronous path (e.g., FF to FF), TA will give an uncertainty which you can plug into the above equation.

This is not able to be constrained as we can only constrain the max delay in FROM-TO. So the hold needs to be manually checked by comparing the fastest path delay reported in the Hold paths under the TS_offset_in FROM-TO constraint to the M value calculated above.

  • fastest path delay >= M : met
  • fastest path delay < M   : not met


Workaround for OFFSET OUT constraint

1. Slowest paths

The OFFSET OUT Slowest paths Slack equation is:


Slowest paths Slack = requirement - (clock arrival + clock path + data path + uncertainty))

In order for this slack >=0, data path delay should not exceed N = (clock arrival + clock path + uncertainty - requirement). So N is the requirement value for the FROM-TO constraint.

  • requirement : this is the OFFSET OUT value
  • clock path : in slowest paths analysis, maximum clock path delay needs to be used. This delay can be seen by doing user-specified endpoint analysis, setting source to the clock input pad and destination to output FF. The maximum clock path delay is given in Setup paths under this path filter analysis. For more information please see (Xilinx Answer 2742)
  • clock arrival : clock arrival is determined by whether the input clock is phase shifted
  • uncertainty : The clock uncertainty can be estimated from timing analyzer if the fclk clocks a synchronous path (e.g., FF to FF), TA will give an uncertainty which you can plug into the above equation.

Then a FROM-TO constraint should be used between the output register and the output pad.

net <output_register_name> TNM = output_reg_grp;
inst <output_pad_name> TNM = output_pad_grp;
TIMESPEC TS_offset_out = FROM output_reg_grp TO output_pad_grp N ns;


2. Fastest paths

The OFFSET OUT Fastest paths Delay equation is :
 
Fastest paths Delay = (clock arrival + clock path + data path - uncertainty)

You can manually calculate the Fastest paths Delay:

  • clock arrival : clock arrival is determined by whether the input clock is phase shifted
  • clock path : in fastest paths analysis, minimum clock path delay needs to be used. This delay can be seen by doing user-specified endpoint analysis, setting source to the clock input pad and destination to output FF. The minimum clock path delay is given in Hold paths under this path filter analysis. For more information please see (Xilinx Answer 2742)
  • data path : this is the fastest path delay reported in the Hold paths under the TS_offset_out FROM-TO constraint
  • uncertainty : The clock uncertainty can be estimated from timing analyzer if the fclk clocks a synchronous path (e.g., FF to FF), TA will give an uncertainty which you can plug into the above equation.
AR# 51100
创建日期 08/17/2012
Last Updated 06/24/2014
状态 Active
Type 已知问题
Tools
  • EDK - 14
  • ISE Design Suite - 14
Boards & Kits
  • Zynq-7000 All Programmable SoC Boards and Kits