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14.x ISE SysGen - CORDIC SinCos block differs between simulink simulation and hardware
When running a design that previously worked in older versions of the tools, the CORDIC SinCos block now gives incorrect outputs in hardware (though it works in simulation).
Why is this happening?
This is a known issue is ISE Sysgen 14.x.
- Use the DDS Compiler block, as it has the same functionality (or even the CORDIC block)
Because the CORDIC SinCos block is part of the reference block set, you can right click it and select 'Look Under Mask' to view the source and make any changes required.
- Use Verilog as the target language instead of VHDL. This will resolve the issue.