UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!
  1. Xilinx -灵活应变. 万物智能.
  2. 技术支持
  3. AR# 51127: 14.4 EDK Libgen does not support external interrupt vector connected to axi_intc

AR# 51127

14.4 EDK Libgen does not support external interrupt vector connected to axi_intc

描述

I tried to connect a vector of three elements to axi_intc. After exporting to SDK and running libgen, I got the following error:

ERROR:EDK - intc () - Internal error: Num intr inputs 3 not the same as length of xget_interrupt_sources 1
ERROR:EDK:3416 - Error(s) while running TCL procedure generate().

解决方案

The workaround is to separate the vector into individual signals and then connect them individually to axi_intc.

Example for external interrupts:

Change from an external interrupt vector:
PORT axi_intc_Intr_pin = axi_intc_Intr, DIR = I, VEC = [2:0], SIGIS = INTERRUPT, SENSITIVITY = EDGE_RISING
To 3 individual ports:
PORT axi_intc_0_Intr_pin = axi_intc_0_Intr, DIR = I, SIGIS = INTERRUPT, SENSITIVITY = EDGE_RISING
PORT axi_intc_1_Intr_pin = axi_intc_1_Intr, DIR = I, SIGIS = INTERRUPT, SENSITIVITY = EDGE_RISING
PORT axi_intc_2_Intr_pin = axi_intc_2_Intr, DIR = I, SIGIS = INTERRUPT, SENSITIVITY = EDGE_RISING
 
And connect them to axi_intc in this way:
PORT Intr = axi_intc_2_Intr & axi_intc_1_Intr & axi_intc_0_Intr
AR# 51127
日期 01/07/2013
状态 Active
Type 已知问题
Tools More Less
IP
的页面