"> AR# 51192: Artix-7 FPGA Initial Engineering Sample (IES) - Known Issues Master Answer Record

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AR# 51192

Artix-7 FPGA Initial Engineering Sample (IES) - Known Issues Master Answer Record

Description

This answer record highlights important requirements and known issues for the Artix-7 FPGA Initial Engineering Sample (ES) program related to software and IP. Additional silicon limitations might exist, so please reference the 7 Series Errata found on xilinx.com.

This answer record will be updated as new information becomes available regarding known issues, patches, IP support, and more. Please check back often for the most current information.

解决方案

Software Requirements
  • ISE Design Suite 14.2 or Vivado Design Suite 2012.2, available on the Xilinx Download Center, is required for use ofInitial ES silicon forArtix-7 devices
  • Patches - this is the complete list of available patches for ISE14.2/Vivado 2012.2software targeting the Artix-7Initial ES silicon
      • Required patches for all users:
        • None
      • Required patches based on usage:
        • None
Software Known Issues
  • (Xilinx Answer 47816) - 7 Series - ISE 14.x/Vivado 2012.2 Design Suite Known Issues Related to 7 Series FPGAs
Other Important Items
Revision History
8/22/2012 - Initial Release

链接问答记录

相关答复记录

Answer Number 问答标题 问题版本 已解决问题的版本
47816 7 Series - ISE 14.x/Vivado 2012.x Design Suite Known Issues Related to 7 Series FPGAs N/A N/A
51017 有关 Artix-7 GTP 收发器加电/断电的设计咨询 N/A N/A
AR# 51192
创建日期 08/07/2012
Last Updated 08/21/2012
状态 Active
Type 已知问题
器件
  • Artix-7
Tools
  • ISE Design Suite - 14.2
  • Vivado - 2012.2