AR# 51192: Artix-7 FPGA Initial Engineering Sample (IES) - Known Issues Master Answer Record
Artix-7 FPGA Initial Engineering Sample (IES) - Known Issues Master Answer Record
This answer record highlights important requirements and known issues for the Artix-7 FPGA Initial Engineering Sample (ES) program related to software and IP. Additional silicon limitations might exist, so please reference the 7 Series Errata found on xilinx.com.
This answer record will be updated as new information becomes available regarding known issues, patches, IP support, and more. Please check back often for the most current information.
ISE Design Suite 14.2 or Vivado Design Suite 2012.2, available on the Xilinx Download Center, is required for use ofInitial ES silicon forArtix-7 devices
Patches - this is the complete list of available patches for ISE14.2/Vivado 2012.2software targeting the Artix-7Initial ES silicon
Required patches for all users:
Required patches based on usage:
Software Known Issues
(Xilinx Answer 47816) - 7 Series - ISE 14.x/Vivado 2012.2 Design Suite Known Issues Related to 7 Series FPGAs