AR# 51200: FIFO Generator 9.2 - Synthesis fails with redeclaration of module
FIFO Generator 9.2 - Synthesis fails with redeclaration of module
If I synthesize a design with a FIFO 9.2 core (Verilog), the following error occurs:
========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "ipcore_dir/fifo_generator_v9_2.v" in library work Compiling verilog file "top.v" in library work Module <fifo_generator_v9_2> compiled Compiling verilog file "ipcore_dir/fifo_generator_v9_2_synth.v" in library work Module <top> compiled ERROR:HDLCompilers:27 - "ipcore_dir/fifo_generator_v9_2_synth.v" line 54 Illegal redeclaration of 'fifo_generator_v9_2' Module <fifo_generator_v9_2> compiled Analysis of file <"top.prj"> failed.
The *_synth.v file is erroneous and should be removed. Please delete this file from the ipcore_dir and "Clean Project Files" and synthesize again. Warnings will appear that the file is now missing, but XST should complete without issue.
Alternatively, to avoid the warning, the issue can be resolved by performing the following:
Remove FIFO core from the ISE project.
Edit the <fifo_core_name>_xmdf.tcl file and comment out the following lines: For VHDL flow utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path <fifo_core_name>_synth.vhd utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl incr fcount For Verilog flow utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path <fifo_core_name>_synth.v utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog incr fcount
Add the FIFO core back in to the project.
This issue has been resolved in version 9.3 of the FIFO Generator.