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AR# 5121

M1.5i/2.1i Timing - What is a Timing Report File (.twr), and what does it contain?

Description

General Description:

What is a timing report, and what information does it contain?

解决方案

NOTE: This report is specific to Virtex, but the explanation applies to all FPGA families.

The header describes the software version, design file, constraint file, and type of report.

"Verbose" lists the paths for each constraint and error list paths for constraints with errors.

The limit controls the number of paths listed for each constraint.

--------------------------------------------------------------------------------

Xilinx TRACE, Version M1.5.25

Copyright (c) 1995-1998 Xilinx, Inc. All rights reserved.

Design file: synpli.ncd

Physical constraint file: synpli.pcf

Device,speed: XCV50,-4 (x1_0.69 1.75 Advanced)

Report level: Verbose report, limited to 1 item per constraint

----------------------------------------------------------------------------------------------

If there are circuit loops in the design, they will be disabled for timing purposes.

The source and destination area of the loops are listed.

-----------------------------------------------------------

196 circuit loops found and disabled.

-----------------------------------------------------------

----------------------------------------------------------------------------------------------------------------

! Warning: The following connections are in combinational loops, and !

! some paths through these connections may not be analyzed. !

!

! Signal...........................Driver....................Load !

! -------------------------------- ----------------------------- ---------------- !

! un0............................GCLKBUF2.OUT.....DLL2.CLKFB !

--------------------------------------------------------------------------------------------------------------

Each constraint is listed, and the following information is displayed:

- The constraint.

- Paths analyzed, end-point errors.

- Minimum delay.

==================================================================

Timing constraint: NET "U_dll_2x_board.un4" PERIOD = 10 nS HIGH 50.000 % ;

196 items analyzed, 0 timing errors detected.

Minimum period is 8.731ns.

---------------------------------------------------------------------------------------------------------------------------

"Slack = Constraint - Skew - Delay"

Slack: 1.269ns path U_zbtcntlr.Data_in0[31] to U_zbtcntlr.Rw_tff[1] relative to

8.705ns total path delay

0.026ns clock skew

10.000ns delay constraint

------------------------------------------------------------------------------------------------------------------------------

"Physical Resource" is the name of the LUT, RAM, FLOP, or LATCH in a CLB, SLICE,

or IOB. This is the BEL name. "Logical Resource" is the name in the source design netlist.

--------------------------------------------------------------------------------------------------------------------------

Path U_zbtcntlr.Data_in0[31] to U_zbtcntlr.Rw_tff[1] contains 2 levels of logic:

Path starting from Comp: CLB_R4C16.S0.CLK (from un0)

To................................Delay type...........Delay(ns)....Physical Resource...........Logical Resource(s)

CLB_R4C16.S0.YQ.....Tcko...................1.383R........U_zbtcntlr.Data_in0[31]...U_zbtcntlr.Rw_tff[0]

CLB_R7C24.S1.BY......net (fanout=33)...6.804R........U_zbtcntlr.Rw_tff[0]

CLB_R7C24.S1.CLK....Tdick................. 0.518R........U_zbtcntlr.Rw_tff[1].........U_zbtcntlr.Rw_tff[2]

-------------------------------------------------

Total (1.901ns logic, 6.804ns route)..........8.705ns (to un0)

(21.8% logic, 78.2% route)

==============================================================================

All constraints were met.

Clock to Setup on destination clock FRAME_CLKB

---------- - - - -----+ - - - - - - - - - +- - - - - - - - - +- - - - - - - - - + - - - - - - - - -+

.......................| Src/Dest.....|...Src/Dest...|...Src/Dest..|...Src/Dest...|

Source Clock |Rise/Rise.....|....Fall/Rise......|Rise/Fall......|Fall/Fall|

------------- - - - - +- - - - - - - - - - + - - - - - - - - -+ - - - - - - - - - + - - - - - - - - -+

ARM_CHNL_B.|...5.249.......|....................|....................|....................|

FRAME_CLKB. |..6.527........|....................|....................|....................|

LOCAL_CLK |...4.216...........|....................|....................|....................|

PIXEL_CLKB |...5.225..........|....................|....................|....................|

This means the Q of a flip-flop that is running on one of the four "source" clocks will reach

the D of a flip-flop that is running on the "destination" clock (in this case FRAME_CLKB) in

no more than "X"ns.

This will list all of the members of groups created by the user:

Table of Time Groups:

---------------------------------------------

TimeGroup DLLS:

Comps:

U_dll_2x_board.U_clkdll_ext

-----------------------------------------------

Timing summary:

----------------------------------------

Timing errors: 0 Score: 0

-----------------------------------------

For more information on the "coverage score," please see (Xilinx Solution 2963).

--------------------------------------------------------------------------------------------------------------------------

Constraints cover 392 paths, 0 nets, and 297 connections (71.6% coverage)

---------------------------------------------------------------------------------------------------------------------------

The "minimum period" is the result of longest path covered by constraints.

-----------------------------------------------------------------------------------------------------

Design statistics:

Minimum period: 8.731ns (Maximum frequency: 114.534MHz)

Analysis completed Tue Dec 01 10:33:11 1998

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AR# 5121
创建日期 08/31/2007
Last Updated 01/18/2010
状态 Archive
Type 综合文章