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AR# 51211

PlanAhead - How can I change PlanAhead HDL target language from Verilog to VHDL or vice-versa?

Description

How can I change the target language (VHDL to Verilogor vice-versa) for a PlanAhead project?

解决方案

There are two ways to do this.

1. While creating a new project in theAdd Sources window, you can change the Target Language as shown below:

ar_PA.png

2. In Project Settings, change the Target Language, as shown below:

ar_PA2.png

AR# 51211
创建日期 12/10/2012
Last Updated 12/10/2012
状态 Active
Type 综合文章
器件
  • FPGA Device Families
Tools
  • PlanAhead