AR# 51211

PlanAhead - How can I change PlanAhead HDL target language from Verilog to VHDL or vice-versa?

描述

How can I change the target language (VHDL to Verilogor vice-versa) for a PlanAhead project?

解决方案

There are two ways to do this.

1. While creating a new project in theAdd Sources window, you can change the Target Language as shown below:

ar_PA.png

2. In Project Settings, change the Target Language, as shown below:

ar_PA2.png

AR# 51211
日期 12/10/2012
状态 Archive
Type 综合文章
器件
Tools