Starting with 2013.2, Vivado Synthesis supports the safe implementation feature via HDL.
As part of this support by the tool, you can set the safe implementation state to either a reset or "power on" state.
For example:
reg [FSM_BITS-1:0] state /*synthesis fsm_safe_state = "reset_state" */
This will tell Vivado Synthesis to use reset_state as a safe state.
If the state machine does not have reset_state or power_on_state, then the safe state will not be implemented.
At present, these are the only safe implementation states supported by the tool.
In future Vivado Synthesis releases, user-specified states will be supported.
AR# 51237 | |
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日期 | 11/26/2014 |
状态 | Active |
Type | 综合文章 |
Tools |