AR# 51237


Does Vivado Synthesis support the FSM Safe Implementation feature?


Does Vivado Synthesis support the FSM Safe Implementation feature?


Starting with 2013.2, Vivado Synthesis supports the safe implementation feature via HDL. 

As part of this support by the tool, you can set the safe implementation state to either a reset or "power on" state.

For example: 

reg [FSM_BITS-1:0] state /*synthesis fsm_safe_state = "reset_state" */

This will tell Vivado Synthesis to use reset_state as a safe state.

If the state machine does not have reset_state or power_on_state, then the safe state will not be implemented.

At present, these are the only safe implementation states supported by the tool. 

In future Vivado Synthesis releases, user-specified states will be supported.


For versions prior to 2013.2, users are requested to add a default state to a finite state machine case statement with -fsm_extraction set to "NO" in order to guarantee that Vivado Synthesis uses the default statement.

Vivado Synthesis will use the default state and redirect invalid or unreachable states using this default clause statement.

If -fsm_extraction is set to Yes, care should be taken to make sure that the FSM has reachable states.

Optimization of the default statement can occur for unreachable states.
AR# 51237
日期 11/26/2014
状态 Active
Type 综合文章
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