AR# 5128

LogiCORE PCI - When is the S_WRDN signal valid?

描述

General Description:

The PCI32 User Guide states that S_WRDN is valid during ADDR_VLD and held through the entire transaction. Is this correct?

解决方案

S_WRDN is sampled on the next clock after the assertion of ADDR_VLD. It indicates a WRITE when asserted High and a READ when asserted Low.

ADDR_VLD is asserted only during the address phase, while S_WRDN remains at a stable value until the end of the transaction.

AR# 5128
日期 12/15/2012
状态 Active
Type 综合文章