Xilinx provides detailed pin-out and banking requirements that are critical to the success of a MIG 7 Series design.
When designing a new memory interface design or debugging an issue encountered in hardware with an existing MIG 7 Series design, it is imperative that the documented pin-out and banking requirements of the 7 Series DDR2/DDR3 design have been followed.
These guidelines can be found in the Design Guidelines sections within the 7 Series FPGAs Memory Interface Solutions User Guide (UG586): http://www.xilinx.com/support/documentation/ipinterconnect_mig-7series.htm
If the MIG 7 Series output design was not modified, these requirements will be followed.
However, if any changes have been made to the UCF, these changes must be verified against the design requirements.
Note: This answer record is part of the Xilinx MIG Solution Center (Xilinx Answer 34243).
The Xilinx MIG Solution Center is available to address all questions related to MIG.
Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.
The MIG 7 Series GUI includes multiple flows for creating memory interface pin-outs as well as verifying changes to previously generated pin-outs.
The 7 series FPGA banks are comprised of four T* byte groups.
Each byte group is made up of 12 I/O.
The general MIG 7 Series design creation flow ("New Design") allows users to select which data or address/control/command groups are assigned to which FPGA bank byte groups.
The "Fixed Pin-Out" design generation flow allows users to manually select each pin or upload a UCF.
The tool will then verify the pins selected, report any warnings/errors, and upon zero reported errors, generates the appropriate MIG 7 Series design.
When pin changes are made to the generated MIG 7 Series UCF, "Verify Pin Changes" and "Update Design flow" can be used to upload the modified UCF and generate a design with the appropriate UCF and rtl parameter settings.
Manually changing or creating a pin-out without using the MIG 7 Series tool for verification is not supported and can lead to unroutable designs or failures in hardware.
Additional Information/Commonly Asked Questions:
(Xilinx Answer 41752) MIG 7 Series DDR3/DDR2 - Can an x16 interface fit into a single bank?
(Xilinx Answer 41706) MIG 7 Series - Can FPGA banks be shared amongst memory interfaces?
(Xilinx Answer 46082) MIG 7 Series DDR3 - How to enable Dynamic ODT special use case to remove need to have an ODT pin on the FPGA
(Xilinx Answer 40603) MIG 7 Series FPGAs DDR3/DDR2 - Clocking Guidelines
(Xilinx Answer 42036) MIG 7 Series - Internal/External VREF Guidelines