描述

This answer record describes the various SystemVerilog data types supported by Vivado Synthesis and also provides coding examples for them. These coding examples are attached to this answer record. The answer record also contains information related to known issues and good coding practices.

Note: Each coding example can be used to directly create a Vivado project. Please refer to the header in each source file for the SystemVerilog constructs covered in each example.

解决方案

SystemVerilog Data Types that are supported in Vivado Synthesis.

The following are the SystemVerilog Data Types that are supported in Vivado Synthesis. Refer to Table 1-1 at the end of this answer record for the coding examples for the data types.

1. Integer Data Types

Vivado Synthesis supports the following Integer SystemVerilog Data Types.

• shortint: 2-state 16-bit signed integer
• int: 2-state 32-bit signed integer
• longint: 2-state 64-bit signed integer
• byte: 2-state 8-bit signed integer
• bit: 2-state, user defined vector size
• logic: 4-state user defined vector size
• reg: 4-state user-defined vector size
• integer: 4-state 32-bit signed integer
• time: 4-state 64-bit unsigned integer

The logic type is equivalent or identical to the "reg" type in Verilog in every way but is more than "reg". The logic data type can be both driven by assign block, output of a port and present inside a procedural block. So logic can be used inplace of reg and wire as normally used in Verilog.

logic a, a1, a2;
assign a = b ^ c;
always @ (c or d) a1 = c + d;
mymodule module(.out(a2), .in(xyz));

2. Real Numbers

Vivado Synthesis supports the following real types.

• real: like double in C
• shortreal: like float in C
• realtime: identical to real

However, only constant real type data is supported in Vivado Synthesis. For example, the following code causes the error, "[Synth 8-502] non-constant real-valued expression is not supported"

input real r;
input int a;
output int y;

always_comb
y = a + int'(r);

3. Void Data Type

A Void type represents no storage. It can be used to define functions that do not return a value.

4. User-Defined Types

Vivado Synthesis supports user-defined types, which are defined using the typedef keyword.

typedef data_type type_identifier {size};

or

typedef [enum, struct, union] type_identifier;

5. Enum Types

Vivado Synthesis supports enum types. Enum data types allow meaningful names to be assigned to numeric quantities. The actual values default to integers starting at 0 and then increase. You can choose your own enumerated values. Enum types are strongly typed. A enum type can only be assigned a defined constant names or another identical enumerated type.

typedef enum { circle, ellipse, freeform } ClosedCurve;
ClosedCurve a, b, c, d;
parameter int e = 2;

assign a = 2; //illegal, must assign a label name
assign b = ellipse; //legal
assign c = e; //illegal, must assign an identical enum type
assign d = ClosedCurve'(2); //legal, SystemVerilog requires to explicitly cast the value when trying to store integer value in an enum.

6. Constants

SystemVerilog and Vivado Synthesis support the following elaboration time Constants:

• parameter: Is the same as the original Verilog standard and can be used in the same way.
• localparam: Is similar to parameter but cannot be overridden by upper-level modules or with defparam.
• const: is global constant and is resolved at the END of elaboration.
  const bit TRUE = 1
• SystemVerilog has another constants type called "specparam", which is used for specifying delay and timing values in specify blocks. This value is not supported in Vivado Synthesis.
  

7. Type Operator

SystemVerilog allows paramterizing data types. This is to define data types in terms of parameters in a module so that different data types can be used for the module by changing the parameter value when instantiating the module. For example:

module my_mod #(parameter type my_param = int)
(//inputs and outputs);
my_param my_sig; //this declares a signal called my_sig that is of type int
......
endmoddule

This is useful in that a level above, my_mod can be instantiated as:
my_mod #(.my_param(shortint)) u0 (<port names>);

8. Casting

Assigning a value of one data type to a different data type is illegal in SystemVerilog. Casting is used for converting one type of data type to another type of data type.

• <type>'(<expression>) : cast expression to different data type
• <size>'(<expression>) : casts expression to a vector size
• <sign>'(<expression>) : casts expression to signed or unsigned
  

Coding examples and the Data Types demonstrated in each example

Table 1-1

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