2. 技术支持
  3. AR# 5134: LogiCORE PCI - During Cadence Verilog-XL simulation, a warning reports: "Timing violation in bic_pci_stm.bic_pci_top..."
  4. AR# 51341: Vivado implementation - Unrouted net between BUFMR and BUFR in same clock region

AR# 51341

Vivado implementation - Unrouted net between BUFMR and BUFR in same clock region

描述

The following CRITICAL WARNING might be seen in a design containing a connection between BUFMR and BUFR in the same clock region that cannot be routed.

Phase 7 Verifying routed nets
CRITICAL WARNING: [Route-54] Net: U0_EVA_IDI1TOP/U0_EVA_QDR2IPC/genblk1.U_QDR3MIG_IDI/u_qdr_phy_top/u_qdr_rld_mc_phy/qdr_rld_phy_4lanes_2.qdr_rld_phy_4lanes/n_cq_n is not completely routed.
CRITICAL WARNING: [Route-54] Net: U0_EVA_IDI1TOP/U0_EVA_QDR2IPC/genblk1.U_QDR3MIG_IDI/u_qdr_phy_top/u_qdr_rld_mc_phy/qdr_rld_phy_4lanes_2.qdr_rld_phy_4lanes/n_cq_p is not completely routed.
CRITICAL WARNING: [Route-7] Design has 2 unroutable pins, potentially caused by placement issues.
Unroutable connection Types:
----------------------------
Type 1 : BUFMRCE.O->BUFR.I
-----Num Open nets: 2
-----Representative Net: Net[21] U0_EVA_IDI1TOP/U0_EVA_QDR2IPC/genblk1.U_QDR3MIG_IDI/u_qdr_phy_top/u_qdr_rld_mc_phy/qdr_rld_phy_4lanes_2.qdr_rld_phy_4lanes/n_cq_n
-----BUFMRCE_X1Y12.O -> BUFR_X1Y25.I
-----Driver Term: U0_EVA_IDI1TOP/U0_EVA_QDR2IPC/genblk1.U_QDR3MIG_IDI/u_qdr_phy_top/u_qdr_rld_mc_phy/qdr_rld_phy_4lanes_2.qdr_rld_phy_4lanes/gen_ibuf_cq.genblk20.bufmr_cqn/O Load Term [5598]: U0_EVA_IDI1TOP/U0_EVA_QDR2IPC/U_BUFR_CQ_N/I

 Verification failed
-----------------------------------------------

 

解决方案

This is due to a hardware limitation for routing resources between BUFMRCE and BUFR in the same clock region.

For this connection to route successfully, an unused PHASER site must be available to route through.

In the case of this Critical Warning, a MIG core was used in the design and so no PHASER was available for the connection.

 
 
AR# 51341
日期 03/23/2015
状态 Active
Type 综合文章
器件
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